This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IPfrom the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGADevice. We have “Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm” on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement. After Completing this course you will be able to: Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLSIntegrating the HLS IP with Video Processing Pipeline with TPG and VDMAand Implementing on the FPGA Device. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer VisionMigrating the OpenCV algorithm into XfOpenCV
